1. Field of the Invention
The present invention relates to a semiconductor device including a transistor and a method for driving the semiconductor device.
2. Description of the Related Art
A process of fabricating a semiconductor device such as a shift register can be simplified when the semiconductor device is composed of transistors of the same conductivity type, for example, composed of only n-channel transistors, as compared to when the semiconductor device is composed of p-channel transistors and n-channel transistors. A circuit that is composed of transistors of the same conductivity type and has a function similar to that of a complementary MOS (CMOS) is sometimes referred to as “unipolar CMOS”. A shift register composed of transistors of the same conductivity type is disclosed in Patent Document 1, for example.
FIG. 7 is a circuit diagram illustrating the configuration of part of the shift register disclosed in Patent Document 1. In the shift register, a plurality of stages 80 illustrated in FIG. 7 can be cascaded. The stage 80 includes a transistor 81, a transistor 82, a transistor 83, a transistor 84, and a capacitor 85. All the transistors (the transistors 81 to 84) included in the stage 80 can be n-channel transistors. Thus, all the transistors included in the shift register can be n-channel transistors.
In the stage 80, a drain of the transistor 81 is connected to a terminal C1 and supplied with a clock signal CLK. A source of the transistor 81 is connected to an output terminal OUT and a drain of the transistor 82. A signal output from the output terminal OUT is an output signal of the stage 80. A gate of the transistor 81 is connected to a source of the transistor 83. A source of the transistor 82 is connected to a terminal VSS and supplied with a low power supply potential (e.g., a ground potential). A gate of the transistor 82 is connected to a terminal C2 and supplied with an inverted clock signal CLKB. The inverted clock signal CLKB is an inversion signal of the clock signal CLK (a signal having a logic level opposite to that of the clock signal CLK). A gate and a drain of the transistor 83 are connected to an input terminal N. The input terminal N is supplied with an output signal of the previous stage 80. The source of the transistor 83 is connected to a drain of the transistor 84. A source of the transistor 84 is connected to the terminal VSS and supplied with the low power supply potential (e.g., the ground potential). A gate of the transistor 84 is connected to the output terminal OUT of the subsequent stage 80. The capacitor 85 is provided between the gate and source of the transistor 81.
In the stage 80, a high-level potential of the output signal is a high-level potential of the clock signal CLK, and a low-level potential of the output signal is the low power supply potential. The shift register including the plurality of stages 80 drives a plurality of loads using output signals that are sequentially output from the plurality of stages 80. For example, when the shift register is used in a scan line driver circuit of a display device, the loads correspond to scan lines, elements connected to the scan lines, and the like.